As an IT (Information Technology) rapidly progresses, a transmission rate of data on a transmission path has become increasingly higher. For that reason, it is demanded that an electrical circuit included in a device connected to the transmission path include a function of performing large-scale and high-speed processing. Accordingly, circuit design which uses a DDR SDRAM has been frequently carried out.
In the DDR SDRAM, a data strobe signal (DQS) is used so as to inform a receiver of a timing for transferring data. The DQS is a bi-directional strobe signal, and functions as an operation reference clock for data input/output when a read/write operation is performed.
In view of data transfer between a memory read control circuit and the DDR SDRAM, it is a common practice to carry out design so that an internal circuit in the memory read control circuit is adjusted in consideration of an external transmission delay. Accordingly, there arises the need for carrying out customized design in consideration of a timing for each application even in a same circuit configuration. Then, a memory read control circuit having versatility, which does not need customized deign according to a product and performs a mask operation of the DQS, has been invented by the inventor of this application (refer to Patent Document 1).
In such a memory read control circuit, it is determined that a data strobe signal has repeated a predetermined number of times of transitions based on information on the number of data reads, and a mask signal is thereby set to a mask state. Accordingly, the data strobe signal is stably mask-controlled irrespective of the number of data reads. As a result, the need for customized design for each product is eliminated. Versatile circuit design therefore becomes possible.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2009-37287A